PLLs are commonly used in (indirect) frequency synthesis applications. A PLL consists of a negative feedback circuit that allows multiplying the frequency of a reference signal by a selected frequency conversion factor; this results in the generation of a tuneable and stable output signal at the desired frequency.
For this purpose, a frequency divider scales the frequency of the output signal by the conversion factor. The resulting frequency-scaled signal is fed back to a phase comparator, which detects a phase difference between the feedback signal and the reference signal. The phase comparator outputs a control current indicative of the detected phase difference. A loop filter integrates the control current into a corresponding control voltage for a Voltage-Controlled Oscillator (VCO), which varies the frequency of the output signal according to the control voltage value.
In a locked condition, the frequency of the feedback signal matches the frequency of the reference signal; therefore, the frequency of the output signal is equal to the reference frequency multiplied by the conversion factor.
A particular architecture (commonly referred to as fractional-N) has become increasingly popular over the years, especially in wireless communication applications working at high frequency. In a fractional-N PLL, differently from an integer-N PLL, the frequency conversion factor N is a non-integer, i.e., a fractional number. To this purpose, the divide factor of the frequency divider is caused to vary dynamically between different integer numbers, for example between two consecutive integers N and N+1, so as to obtain the desired, fractional average conversion factor.
The fractional-N PLL architecture allows overcoming the known limitations of integer-N PLLs, which are characterized by a trade-off between bandwidth, settling time, frequency spacing, phase noise, and power consumption.
Typically, a fractional-N PLL includes an accumulator that continuously adds to itself an adjusting value, defining a fractional component of the desired frequency conversion factor. As long as the content of the accumulator is lower than its capacity (corresponding to the maximum allowed adjusting value), the frequency divider is caused to divide the frequency of the PLL output signal by an integer component N of the fractional conversion factor; each time the accumulator overflows, the frequency divider is caused to increment the divide factor by one unit (N+1). In other words, the frequency divide factor is modulated.
A problem of fractional-N PLLs is that the feedback signal and the reference signal, even in the locked condition, are not instantaneously at the same frequency, but only so on average; the frequency difference between the two signals translates into a phase error having a value that varies with the same periodicity as the variation of the frequency-divider divide factor. The periodicity of the variation of the phase error introduces spurious signals (shortly referred to as spurs) rather close to the frequency of the PLL output signal, the frequency offsets of the spurs from the output signal frequency corresponding to harmonics of the periodicity of the modulation pattern for the frequency divider.
A known technique for reducing the energy level of the spurs calls for compensating the above-mentioned phase error. This technique is based on the consideration that the accumulator used to control the divide factor of the frequency divider actually behaves as a phase-error accumulator and, in the locked condition, the value in the accumulator represents the phase error between the feedback signal and the reference signal. The content of the accumulator, properly scaled, is thus converted by a Digital-to-Analog Converter (DAC) into a corresponding compensation current, that is added to the control current generated by the phase comparator.
A problem of the above-mentioned phase-error compensation technique relates to the resolution required for the DAC generating the compensation current. In principle, a DAC having the same number of bits as the counter in the accumulator needs to be employed. The number of bits of the accumulator is related to the number of different channels that can be selected, and can be very high; for example, it may be necessary to have 216 or even 220 different channels, so that accumulators of sixteen bits or even twenty bits are needed.
Designing and implementing a multibit DAC with such a high level of resolution is a challenging and almost impractical task; just to cite one problem, the power consumption of such a DAC would be very high.